ERROR:EDK:4182, ERROR:EDK:4075 & 4073 Miscellaneous Errors that occur when adding cores

So I ran into some interesting errors when adding simple cores to my design. On ISE13.2 working with the ML510 I encountered these errors when adding one simple core. 

At first I started out with a set of errors that looked like this:

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ERROR:EDK:4182 - PORT:PLB_masterID - VEC evaluation of (C_SPLB_MID_WIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\data_checker_v1_00_a\data\data_checker_v2_1_0.mpd line 51

ERROR:EDK:4182 - PORT:PLB_BE - VEC evaluation of ((C_SPLB_DWIDTH/8)-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\data_checker_v1_00_a\data\data_checker_v2_1_0.mpd line 55

ERROR:EDK:4182 - PORT:PLB_wrDBus - VEC evaluation of (C_SPLB_DWIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\data_checker_v1_00_a\data\data_checker_v2_1_0.mpd line 60

ERROR:EDK:4182 - PORT:Sl_rdDBus - VEC evaluation of (C_SPLB_DWIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\data_checker_v1_00_a\data\data_checker_v2_1_0.mpd line 76

ERROR:EDK:4182 - PORT:PLB_masterID - VEC evaluation of (C_SPLB_MID_WIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\rx_serdes_v1_00_a\data\rx_serdes_v2_1_0.mpd line 57

ERROR:EDK:4182 - PORT:PLB_BE - VEC evaluation of ((C_SPLB_DWIDTH/8)-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\rx_serdes_v1_00_a\data\rx_serdes_v2_1_0.mpd line 61

ERROR:EDK:4182 - PORT:PLB_wrDBus - VEC evaluation of (C_SPLB_DWIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\rx_serdes_v1_00_a\data\rx_serdes_v2_1_0.mpd line 66

ERROR:EDK:4182 - PORT:Sl_rdDBus - VEC evaluation of (C_SPLB_DWIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\rx_serdes_v1_00_a\data\rx_serdes_v2_1_0.mpd line 82
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 To get around this, most of the time you see a VEC evaluation failed, you can just hardcode the values in the .mpd file to what they should be. When you do this you clear these but you get another set of errors as depicted below.

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ERROR:EDK:4075 - INSTANCE: DDR2_SDRAM_DIMM1, PORT: SPLB0_Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v6_04_a\data\mpmc_v2_1_0.mpd line 1013
ERROR:EDK:4075 - INSTANCE: PCI32_BRIDGE, PORT: Sl_RdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pci_v1_04_a\data\plbv46_pci_v2_1_0.mpd line 191
ERROR:EDK:4075 - INSTANCE: SysACE_CompactFlash, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\data\xps_sysace_v2_1_0.mpd line 121
ERROR:EDK:4075 - INSTANCE: mdm_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 159
ERROR:EDK:4075 - INSTANCE: xps_intc_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_01_a\data\xps_intc_v2_1_0.mpd line 130
ERROR:EDK:4075 - INSTANCE: blink_test_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Users\user1\Documents\Projects4\v2\pcores\blink_test_v1_00_a\data\blink_test_v2_1_0.mpd line 72

ERROR:EDK:4075 - INSTANCE: data_gen_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Users\user1\Documents\Projects4\v2\pcores\data_gen_v1_00_a\data\data_gen_v2_1_0.mpd line 75

ERROR:EDK:4075 - INSTANCE: tx_serdes_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Users\user1\Documents\Projects4\v2\pcores\tx_serdes_v1_00_a\data\tx_serdes_v2_1_0.mpd line 79

ERROR:EDK:4073 - INSTANCE: mb_plb, PORT: PLB_BE, CONNECTOR: mb_plb_PLB_BE - 16 bit-width connector assigned to 8 bit-width port - C:\Users\user1\Documents\Projects4\v2\_xps_tempmhsfilename.mhs line 112

ERROR:EDK:4073 - INSTANCE: mb_plb, PORT: PLB_masterID, CONNECTOR: mb_plb_PLB_masterID - 3 bit-width connector assigned to 2 bit-width port - C:\Users\user1\Documents\Projects4\v2\_xps_tempmhsfilename.mhs line 112

ERROR:EDK:4073 - INSTANCE: mb_plb, PORT: PLB_wrDBus, CONNECTOR: mb_plb_PLB_wrDBus - 128 bit-width connector assigned to 64 bit-width port - C:\Users\user1\Documents\Projects4\v2\_xps_tempmhsfilename.mhs line 112
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These errors are fairly bizarre since I didn't really touch anything. To fix the errors, simply ignore the beginning ones about VEC signal out of range, and jump straight to the last ones at the end about the PORTS. The trick is to manually change the the widths in the .mpd to the values the errors are requesting.

Reconfiguring Zynq Processing System Settings and Clocks

I thought I would post this because someone was asking me about the Zynq FCLKs today. To determine the max frequency of the Zynq clocks you can access the "Clock Wizard" in XPS. You can customize and configure much of the pre-defined cores that are automatically added to most Zynq projects from the "Zynq" tab:

To check out the clock settings, click the box that says "Clock Generation" this core specifically configures the PS to PL available clocks.
Once you click this the "Clock Wizard" will appear. You can now see what the frequencies of the different clocks are.