So this super obscure error is caused by having a clk routed within a PR region. I found an AR record that discussed this here (http://forums.xilinx.com/t5/Design-Planning/Partition-output-pin-BramClk-must-be-driven-by-logic-internal-to/td-p/171508):
The basic idea is do not have a clock as an output. You will get this error if you EVER have a clock that is an output but is not connected at some point, like chained reconfigurable regions.
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