ISE Project Navigator crashes opening up a project

As stated in the subject, I ended up finding the solution here:
https://forums.xilinx.com/t5/Design-Entry/ISE-12-3-crashing-on-file-open/td-p/107305

Running Windows 10 x64, Xilinx ISE 14.7

Pasted below for posterity
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For everyone trying to use Xilinx ISE 14.5 in Windows 8 x64.

Rename libPortability.dll to libPortability.dll.orig, and copy libPortabilityNOSH.dll to libPortability.dll.

Do this in:
C:\Xilinx\14.5\ISE_DS\ISE\lib\nt64
C:\Xilinx\14.5\ISE_DS\common\lib\nt64 (copy dll from first location)

This turns off SmartHeap.

This will fix ISE and iMPACT crashes on file dialogs.
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Xilinx Product Licensing Page

I can't ever find it :(

https://secure.xilinx.com/webreg/login.do?goto=https%3A%2F%2Fsecure.xilinx.com%3A443%2Fwebreg%2Fregister.do%3Fgroup%3Desd_oms%26tab%3DCreateLicense

How install Xilinx tools if the Accessories folder is missing

Turns out you can uninstall through the Xilinx Information Center > Manage Installs, if you don't have the installer around.

Xilinx Vivado 2015.4 Won't Uninstall

I had a hugely fucked up Xilinx Install apparently. The accessories folder was not there, and when I tried to uninstall I got this:

The Program can't start because MSVCR110.dll is missing from your computer. Try reinstalling the program to fix this problem

Solution

Download the x86 version of this file: Link

Source: Link

Xilinx SDK Vivado Issues

Had a new Xilinx Issue with Vivado 2015.4 after a hard drive failed and I had to revert to a back-up clone:

In a project that previously already worked I got

"The following errors were found parsing \directory\system.mss"

In a brand new project, the BSP fails creation of a ton of files giving errors like this:

make[1]: *** [xadcps_sinit.o] Error 1

make[1]: Target `libs' not remade because of errors.

make: *** [ps7_cortexa9_1/libsrc/xadcps_v2_2/src/make.libs] Error 2

 Finally, when trying to create a hello world project I got this:

"The STDOUT parameter is not set on the OS. Hello World requires stdout to be set."

Unfortunately, Google had nothing for me, I did a full reinstall and it works after that. yay fpga development. fml.

--------------------------

Edit. Turns out it is NOT the Xilinx installation. I was using a custom BSP build for standalone that was designed for AMP on the Xilinx forums. I was just unlucky because I had never tried to create a project that wasn't designed to be "Empty" which is the only setting it worked on. For reference Xilinx labels this as standalone_v5_39, you just click on BSP settings and there is a drop down menu to edit. 

Error: Failed to save the Vivado user preferences file.

CRITICAL WARNING: [Common 17-741] No write access right to the local Tcl store at '/home/user1/.Xilinx/Vivado/2015.4/XilinxTclStore'. XilinxTclStore is reverted to the installation area. If you want to use local Tcl Store, please change the access right and relaunch Vivado.
ERROR: [Common 17-1257] Failed to create directory '/opt/Xilinx/Vivado/2015.4/tclapp'.
start_gui
Error: Failed to save the Vivado user preferences file. Reason: '/home/user1/.Xilinx/Vivado/2015.4/vivado.ini (Permission denied)'
Failed to create the shortcut directory: '/home/user1/.Xilinx/Vivado/2015.4/shortcuts'
Failed to create the layout directory: '/home/user1/.Xilinx/Vivado/2015.4/layouts/application'
Failed to create the commands directory: '/home/user1/.Xilinx/Vivado/2015.4/commands'
Failed to create the layout directory: '/home/user1/.Xilinx/Vivado/2015.4/layouts/'
Failed to create directory: /home/user1/.profile
Error: Failed to save the Vivado user preferences file. Reason: '/home/user1/.Xilinx/Vivado/2015.4/vivado.ini (Permission denied)'
Error: Failed to save the Vivado user preferences file. Reason: '/home/user1/.Xilinx/Vivado/2015.4/vivado.ini (Permission denied)'

Reference AR

Fixed everything by:

•  Open Terminal
• Changing Directory to .Xilinx in the home directory
• Change Directory to /Vivado 
• running sudo chmod -R 777 *

[Upgrade Selected] button in IP Status / Report IP is Grayed Out

So I made a quick change to my IP and found that the [upgraded selected] button was greyed out. As a typical Xilinx debug solution, exiting out of Vivado and reloading was the solution This AR report hints that whenever something is greyed out there is possibly a problem with the license.

Planahead 14.7: Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)

May this be a lesson to future engineers working on critical applications. Always document your work especially right after crunch time. I ran into a problem with Xilinx Tools over a full year ago and managed to solve the issue. Skip forward to present day, I forgot I had solved the issue and then had to go through a huge painful process to re-solve it.

Problem: When I open a specific project ISE14.7 Crashes immediately only leaving the following message in the cmd window:

--------------------------------------------------------------------------------------

Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check 'C:/Users/user1/AppData/Roaming/Xilinx/PlanAhead/hs_err_pid7568.l
og' for details
--------------------------------------------------------------------------------------

When I check the log I see this:

--------------------------------------------------------------------------------------

#
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
#
Stack:
no stack trace available, please use hs_err_<pid>.dmp instead.

--------------------------------------------------------------------------------------

Turns out, that the solution is to roll back to a different version of the tools, for me, synthesizing in 14.7 and implementing in 14.2 worked out fine.

Hardware Platform does not update in Xilinx SDK after Export to SDK is selected

Been having an issue where I export to SDK but the bitstream and the hardware platform is not updating correctly. Xilinx has an AR record for this, but they don't have a solution to update the platform, they just tell you a work around, see below:

AR# 36390
12.1 EDK - Export to SDK does not update the bit file in the workspace if hardware XML is not updated


Description
When only the UCF file is modified in the EDK project, the "Export to SDK" function updates the new bit file in the "SDK\SDK_Export" directory. However, the bit file in "SDK\SDK_Workspace_35\hw_platform_0" is not updated. Since "SDK\SDK_Workspace_35\hw_platform_0" is the default directory that "Program FPGA" takes, the FPGA function did not change if you program FPGA within SDK after the export.
Solution
To work around this issue, you can perform either of these steps manually:
Point the "Program FPGA" to the bit file in the EDK project implementation directory, or the SDK\SDK_Export directory.
Copy the bit file from SDK\SDK_Export toSDK\SDK_Workspace_35.

DIFF_TERM does not show up on .pad report

I was trying to add internal device differential termination to my design over pre-existing differential pairs.

I was following the 7 Series SelectIO Resource Guide which said:

"The DIFF_TERM attribute can be specified in the UCF constraints file or by setting the appropriate value in the generic map (VHDL) or in-line parameter (Verilog) of the instantiated IBUFDS, IBUFGDS, IBUFDS_DIFF_OUT, or IOBUFDS_DIFF_OUT primitives."

I tried adding the DIFF_TERM as an INST in the Constraints file but I didn't see anything happen in the .pad report. Turns out that this is a bug and you can actually set DIFF term in the UCF, the .pad report won't ever report it. I found:

http://forums.xilinx.com/t5/7-Series-FPGAs/How-do-I-know-if-DIFF-TERM-is-set-to-be-TRUE-correctly-in-Vivado/td-p/454472

and another link, which both suggested to check the pad's properties to see if it was checked.

I also confirmed that for the pins I did NOT add DIFF_TERM, they did not have the box checked.


Lastly, when I added the DIFF_TERM I made a new entry with INST replacing net for the same name:

http://forums.xilinx.com/t5/Timing-Analysis/NET-vs-INST/td-p/218287

Export Bistream Setting Greyed out when Implementation is open

So 14.7 does this annoying thing where you cannot export the bitstream unless the implementation is open, it gets even worse where sometimes you can have the option still greyed out even if the implementation is open, when this happens the tools didn't make the run you wanted the active run so you need to change it to be able to export

Error: EDK:3759 AddressGen MHS

ERROR:EDK:3759 - AddresGen MHS Error Address Generator can not generate address map for your design. Please check if there is address conflict, clear the conflict and re-generate the address map.Please consult the online help for how to let Address Generator to overwrite the address. If Address Generator still can not generate the address map, please provide the address map manually.
axi_plbv46_bridge_1 has been deleted from the project


So the setup here is I was try to add one normal core that just connects to an axi, and then another core that connects to a plb that also connects to an axi, so axi-to-plb bridge

ISE 14.7

Here are the steps to make it work:

1. Add just the core that only connects the that axi first and then click the address gen button
2. For the Axi-to-plb bridge core, first add the core, set the address
3. Then add the bridge, the bridge MUST be connected to the same interconnect as any other bridges of the same type

Yea this one is frustrating. 

Xilinx SDK Running .elf on the DDR

So I was having problems with this earlier.

The program I was running was too big to fit in the BRAM:

ERROR:EDK:3165 - elfcheck failed!
The following sections did not fit into Processor BRAM memory:
 Section .data (0x420109C0 - 0x42012587)
 Section .rodata (0x4200FF10 - 0x420109BB)
 Section .dtors (0x4200FF08 - 0x4200FF0F)
 Section .ctors (0x4200FF00 - 0x4200FF07)
 Section .fini (0x4200FEE0 - 0x4200FEFF)
 Section .init (0x4200FEA4 - 0x4200FEDF)
 Section .text (0x42000000 - 0x4200FEA3)

Try using the linker script generation tools to generate an ELF that maps
correctly to your hardware design.

 So That is kind of annoying, you now have two options, either 1) make the bram bigger or 2) run it in the DDR

I found the following posts, all kind of describing what was needed to run it in the DDR.

1. Link1
2. Link2
3. Link3

Here is what worked for me:

1. Make sure to generate a new linker with everything in the DDR
2. Program the system.bit and system.bmm with the "Program FPGA" button, make sure that for the "software configuration" that "bootloop" is selected
3. Open the XMD with Xilinx Tools >  XMD Console 
4. when it opens you should have seen a programming FPGA status line: "Fpga Programming Progress....10......etc
5. Type in the following commands

For the Power PC

connect ppc hw  
cd "c:\Location_to_your_software_debug_folder"
dow "your_elf_file" 
con

remember that if the processor is acting weird you can always do a
connect ppc hw; stop; rst -processor

then continue on from dow

Xilinx running someone else's SDK Project

Recently, I had a problem with someone giving me an SDK project.

Here are some useful steps to getting their crap to work

1. Make sure you have your license server on or the bsp will not build
2. If the bsp does not build create a new "Hello World" project and BSP
3. Go to Xilinx Tools > "Repositories" and add in their custom MyProcessorIPLib to nab their drivers
4. Right click on the BSP and "Board Support Package Settings" Make sure the Correct "Supported Libraries" are checked off 
5. Click on the "Drivers" tab and make sure all the correct drivers are loaded instead of the generic 
6. Copy over their source files 
7. Rebuild the project

printf & xil_printf statements break when printing values

I was doing some dev work on the ML507 and I kept running into this problem where the printf statements would not print variables using stuff like %08x and %d etc...

Turns out I needed to change the size of the stack and heap to 0x2000 from 0x400.

more of this error detailed here: Link!

lscript.ld:228 cannot move location counter backwards

 I ran into this and had absolutely no freaking clue what the hell was going on.
 
**** Build of configuration Debug for project spw_int_test ****

make all
Building target: spw_int_test.elf
Invoking: PowerPC gcc linker
powerpc-eabi-gcc -Wl,-T -Wl,../src/lscript.ld -L../../hello_world_bsp_0/ppc440_0/lib -mcpu=440 -mfpu=dp_full -o"spw_int_test.elf"  ./src/helloworld.o ./src/platform.o ./src/spacewire_driver.o  
../src/lscript.ld:228 cannot move location counter backwards (from fffff170 to 00000170)
collect2: ld returned 1 exit status
make: *** [spw_int_test.elf] Error 1

I ended up finding a solution here Link

Simply Change the stack and heap size to 0x400!

Xilinx SDK Processor Folder with Includes Dissapears from BSP!

So, Just as a quick reference, if your BSP does not seem to be building the files for the processor and the normal things you have in the include folder, one of the reasons this happened to me is I was remoted in and lost connection to the license server

Hilarious Xilinx Capitalization Error

So funny story, ran into this crazy xilinx error:

ERROR:EDK - IPNAME:[IPName] INSTANCE:IPNAME_0 - C:\Users\[location]\l.srcs\sources_1\edk\module_1\dump.mhs line 518 - Invalid ip name. IP name cannot have upper case characters.





This is that your actual IP core name cannot have any capital letters when you actually use the peripheral creation wizard. GAH!

14.7 PlanAhead - [Constraints 18-5] Cannot loc terminal "XX_n" at site XX; loc is blocked

So this is a pretty annoying error. The solution is detailed

here:AR# 43315

and here also discusses it: Xilinx Forums

Under the [Project Manager] on the Left side of plan ahead, go to "Implementation Settings"

Under the Section for [Translate (ngdbuild)]  go to "More Options*" and type in:

-uc filelocation

^ use forward slashes / for the location like C:/Users/Xilinx/system.ucf

You MUST remove the constraints file from the project too to get the warnings to disappear.

Error: [Common 17-36] Cannot write file [project_constraints.ucf]

http://forums.xilinx.com/t5/Hierarchical-Design/PlanAhead-cannot-write-to-ucf-during-runs/td-p/271092


I ran into this when I was copying over projects and just modifying the constraints. The solution is to: A workaround for this specific issue is to uncheck "Read- only" for the UCF file that resides in the folder <project_name>.runs/impl_1/.constrs

>> 11/25 Update

Okay this also sometimes happens to me even when the Read-Only IS unchecked, when that happens, I saw one poster that deleted the folder for the run (impl_1 typically) I just made a new run and it will go.