I got this error the other day and it really caused me a lot of frustration. I was only building a simple core too.
Anyway I found this AR which would lead me to solving it http://www.xilinx.com/support/answers/38239.htm
I was frustrated because I could synthesize the lower blocks with no trouble, but the second I put them all into a top level it synthesized half the design away.
The bottom line is a lot of my logic was synthesized out and I am unhappy. Turns out it had to do with my output and I was connecting it to the wrong place because the controller basically would need the output from a different signal.
the TLDR: If You get this you messed up your logic, possibly in a top level because of a sm controller
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