Export Bistream Setting Greyed out when Implementation is open

So 14.7 does this annoying thing where you cannot export the bitstream unless the implementation is open, it gets even worse where sometimes you can have the option still greyed out even if the implementation is open, when this happens the tools didn't make the run you wanted the active run so you need to change it to be able to export

Error: EDK:3759 AddressGen MHS

ERROR:EDK:3759 - AddresGen MHS Error Address Generator can not generate address map for your design. Please check if there is address conflict, clear the conflict and re-generate the address map.Please consult the online help for how to let Address Generator to overwrite the address. If Address Generator still can not generate the address map, please provide the address map manually.
axi_plbv46_bridge_1 has been deleted from the project


So the setup here is I was try to add one normal core that just connects to an axi, and then another core that connects to a plb that also connects to an axi, so axi-to-plb bridge

ISE 14.7

Here are the steps to make it work:

1. Add just the core that only connects the that axi first and then click the address gen button
2. For the Axi-to-plb bridge core, first add the core, set the address
3. Then add the bridge, the bridge MUST be connected to the same interconnect as any other bridges of the same type

Yea this one is frustrating. 

Xilinx SDK Running .elf on the DDR

So I was having problems with this earlier.

The program I was running was too big to fit in the BRAM:

ERROR:EDK:3165 - elfcheck failed!
The following sections did not fit into Processor BRAM memory:
 Section .data (0x420109C0 - 0x42012587)
 Section .rodata (0x4200FF10 - 0x420109BB)
 Section .dtors (0x4200FF08 - 0x4200FF0F)
 Section .ctors (0x4200FF00 - 0x4200FF07)
 Section .fini (0x4200FEE0 - 0x4200FEFF)
 Section .init (0x4200FEA4 - 0x4200FEDF)
 Section .text (0x42000000 - 0x4200FEA3)

Try using the linker script generation tools to generate an ELF that maps
correctly to your hardware design.

 So That is kind of annoying, you now have two options, either 1) make the bram bigger or 2) run it in the DDR

I found the following posts, all kind of describing what was needed to run it in the DDR.

1. Link1
2. Link2
3. Link3

Here is what worked for me:

1. Make sure to generate a new linker with everything in the DDR
2. Program the system.bit and system.bmm with the "Program FPGA" button, make sure that for the "software configuration" that "bootloop" is selected
3. Open the XMD with Xilinx Tools >  XMD Console 
4. when it opens you should have seen a programming FPGA status line: "Fpga Programming Progress....10......etc
5. Type in the following commands

For the Power PC

connect ppc hw  
cd "c:\Location_to_your_software_debug_folder"
dow "your_elf_file" 
con

remember that if the processor is acting weird you can always do a
connect ppc hw; stop; rst -processor

then continue on from dow

Xilinx running someone else's SDK Project

Recently, I had a problem with someone giving me an SDK project.

Here are some useful steps to getting their crap to work

1. Make sure you have your license server on or the bsp will not build
2. If the bsp does not build create a new "Hello World" project and BSP
3. Go to Xilinx Tools > "Repositories" and add in their custom MyProcessorIPLib to nab their drivers
4. Right click on the BSP and "Board Support Package Settings" Make sure the Correct "Supported Libraries" are checked off 
5. Click on the "Drivers" tab and make sure all the correct drivers are loaded instead of the generic 
6. Copy over their source files 
7. Rebuild the project

printf & xil_printf statements break when printing values

I was doing some dev work on the ML507 and I kept running into this problem where the printf statements would not print variables using stuff like %08x and %d etc...

Turns out I needed to change the size of the stack and heap to 0x2000 from 0x400.

more of this error detailed here: Link!

lscript.ld:228 cannot move location counter backwards

 I ran into this and had absolutely no freaking clue what the hell was going on.
 
**** Build of configuration Debug for project spw_int_test ****

make all
Building target: spw_int_test.elf
Invoking: PowerPC gcc linker
powerpc-eabi-gcc -Wl,-T -Wl,../src/lscript.ld -L../../hello_world_bsp_0/ppc440_0/lib -mcpu=440 -mfpu=dp_full -o"spw_int_test.elf"  ./src/helloworld.o ./src/platform.o ./src/spacewire_driver.o  
../src/lscript.ld:228 cannot move location counter backwards (from fffff170 to 00000170)
collect2: ld returned 1 exit status
make: *** [spw_int_test.elf] Error 1

I ended up finding a solution here Link

Simply Change the stack and heap size to 0x400!

Xilinx SDK Processor Folder with Includes Dissapears from BSP!

So, Just as a quick reference, if your BSP does not seem to be building the files for the processor and the normal things you have in the include folder, one of the reasons this happened to me is I was remoted in and lost connection to the license server

Hilarious Xilinx Capitalization Error

So funny story, ran into this crazy xilinx error:

ERROR:EDK - IPNAME:[IPName] INSTANCE:IPNAME_0 - C:\Users\[location]\l.srcs\sources_1\edk\module_1\dump.mhs line 518 - Invalid ip name. IP name cannot have upper case characters.





This is that your actual IP core name cannot have any capital letters when you actually use the peripheral creation wizard. GAH!

14.7 PlanAhead - [Constraints 18-5] Cannot loc terminal "XX_n" at site XX; loc is blocked

So this is a pretty annoying error. The solution is detailed

here:AR# 43315

and here also discusses it: Xilinx Forums

Under the [Project Manager] on the Left side of plan ahead, go to "Implementation Settings"

Under the Section for [Translate (ngdbuild)]  go to "More Options*" and type in:

-uc filelocation

^ use forward slashes / for the location like C:/Users/Xilinx/system.ucf

You MUST remove the constraints file from the project too to get the warnings to disappear.

Error Launching PTC Windchill Quality Solution

Error:

Could not connect to net.tcp://[host]:[port]/Relex.Security/IAccessManager. The connection attempt lasted for a time span of ##:##:##.#######. TCP error code 10061: No connection could be made because the target machine actively refused it.

When I was googling around for this error all I could get were comments on SQL server. The solution is to restart some PTC services that have been turned off:

Error: [Common 17-36] Cannot write file [project_constraints.ucf]

http://forums.xilinx.com/t5/Hierarchical-Design/PlanAhead-cannot-write-to-ucf-during-runs/td-p/271092


I ran into this when I was copying over projects and just modifying the constraints. The solution is to: A workaround for this specific issue is to uncheck "Read- only" for the UCF file that resides in the folder <project_name>.runs/impl_1/.constrs

>> 11/25 Update

Okay this also sometimes happens to me even when the Read-Only IS unchecked, when that happens, I saw one poster that deleted the folder for the run (impl_1 typically) I just made a new run and it will go.

UART not responding on working SDK project and Bitstream

When you need UARTs to connect to peripheral devices as well as UARTs to the terminal, you can run into many confusing situations. In my case I was getting no UART output. One of the things that worked for me was modifying the bsp settings

See the steps below:

Program FPGA Failed: DONE bit didn't go high after programming FPGA

So I ran into this problem for the first time today:

The issue ended up being that while debugging I had to relaunch the SDK and it auto defaulted to the wrong bitfile, so the entire time I was attempting to program the wrong bitstream.

This can also happen if you were previously automatically booting from Linux like with a NAND or something, just program again 

Failed to launch program edif2ngd

[NgdBuild 527] Failed to launch program edif2ngd: The pipe has been ended.

[NgdBuild 28] edif2ngd did not successfully complete.  Please check preceding errors for root cause.

 

This error sucked. Turns out you just need to re-launch the implementation run again. Didn't do anything special.

 

FPGA configuration encountered errors. Program FPGA failed

In this case the solution was actually simple. The console window was actually displaying something like this:

The following sections did not fit into Processor BRAM memory:
Section .jcr (0x88000944 - 0x88000947)
Section .eh_frame (0x88000940 - 0x88000943)
Section .data (0x88000830 - 0x8800093F)
Section .rodata (0x88000814 - 0x88000829)
Section .dtors (0x8800080C - 0x88000813)
Section .ctors (0x88000804 - 0x8800080B)
Section .fini (0x880007E8 - 0x88000803)
Section .init (0x880007B4 - 0x880007E7)
Section .text (0x88000000 - 0x880007B3)

Try using the linker script generation tools to generate an ELF that maps
correctly to your hardware design.

Which is a common error. Normally you can just make the BRAM larger in the EDK and regenerate. If it is still not working other things to try:

Booting from somewhere else:
 http://www.xilinx.com/support/answers/43414.htm
Turning off ELF check if the ELF is too large:
http://www.xilinx.com/support/answers/38178.html
Completely deleting Linker Script and regenerating:
http://forums.xilinx.com/t5/Embedded-Development-Tools/elfcheck-failed/td-p/307699
"It looks like it's still trying to place the data and code into your BRAM.  Double check your linker script generation and manually delete the .ld file before rebuilding the workspace."

Failed to connect to Xilinx hw_server

Program FPGA failed

Reason:

   Failed to connect to Xilinx hw_server. Check if the hw_server is running and correct TCP port is used.

http://www.xilinx.com/support/answers/55431.htm

hw_server is used with the TCF infrastructure for debugging and it only supports Digilent and has to be launch manually from a shell.

The 'Auto Detect' option always chooses the TCF flow when the Digilent cable is plugged in.

If you do not want to use the TCF infrastructure, you must change the JTAG cable pull-down menu from Auto Detect to 'Digilent USB Cable' and resolve the error.

This change is found from SDK's Xilinx Tools -> Configure JTAG Settings. Again, changing from Auto Detect to Digilent USB Cable resolves the issue.

Editing Telemetry Packets for Vector File Testbench in Word

So I you have a packet that looks like this:

AA BB CC DD  11 22 33 44

And you need it to be in a vector read-in format for the simulator

AA
BB
CC
DD
11
22
33
44

You can actually use word find and replace. In this case replace any Two space with just one. And then replace all spaces with ^l

You can also find this setting under the "Special Characters" Button at the bottom of the Find and Replace Menu.

Also note you can use CTRL+SHIFT+8 to see the editing special characters

HDL:Compiler:104:104 - "path" Line XXX: Cannot find in library

So you typically get this error when importing an EDK created core into the ISE. You need to have the design include these libraries, to do this do:

1. Go to the  <Libraries> Tab
2. Type in the exact Library Name
3. in the Library Files location you actually need to go there, it will look something like /path/to/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/
4. It should find all the files and you are good to go

 

Steam Error Code: -130 Failed to load web page / steam needs to be online to update

Hi all,

A friend of mine recently got a pretty terrible virus. After removing everything I discovered his steam also seemed to be broken. On the Steam "Ads" popup as well as the main page I would get the following errors:

Error Code: -130  Failed to load web page (unknown error). 

steam needs to be online to update. please confirm your network connection and try again

 

 

it turns out you can correct these simply by doing the following: 

 

Chrome Settings > Show Advanced Settings > Network > Change Proxy Settings > Lan Settings > Deselect ProxyCheckbox

 

I guess the viruses turned on some proxy...

Xilinx SDK Error Launching Program: Error while running ps7_init method

Sometimes I get this message:

Error Launching Program

Unexpected error while launching program Error while running ps7_init method:

Typically, this happens to me after I have copied a project in ISE over to my computer or overwritten some files.

The things you should check are:

• You have the system.bit bitstream selected
• When you go to Run as> Run Configurations> Xilinx C/C++ ELF go to the Device Initialization tab, and browse/refresh the .tcl even if it is correct

Canceling a bid on Ebay

Someone recently wanted to cancel a bid they placed. I actually had to look this up. To do this, click on your item, the click on the (#) number of bids. It should bring up the bidding history page. At the bottom of the page click on "See how to cancel bids" Go to that link and fill out the Item #, User ID, and a quick reason.

Just future reference stuff for me....

Photoshop Elements: Additional Resources

Some Great Manga Brushes Compilation:

http://www.deviantart.com/?order=9&q=manga+brush

http://manga-apps.deviantart.com/gallery/?set=25579531&offset=48

Also Location for brushes

C:\Program Files (x86)\Adobe\Photoshop Elements 10\Presets\Brushes

Photoshop Elements: Photo to Line art Steps

Filter > Noise > Despeckle
Filter > Blur > Gaussian
Enhance > AutoSharpen
Enhance > Black and White > Vivid Landscapes
Filter > Stylize > Find Edges
Filter > Artistic > Poster Edges
Set Opacity to 50%

Scenic Landscape

Photoshop Elements: Removing Objects from the Scene

Best Reference I could find uses the Healing Tool:

http://photoshopelementstips.blogspot.com/2011/04/how-to-remove-object-from-scene-and.html

Photoshop Elements: Cropping just One Layer

• Use the Rectangle Marquee to select the portion of the layer you want to crop
• Right Click > Select Inverse
• Now Delete! 

Photoshop Elements: Could not complete your request because the smart object is not directly editable

If you get this error:

Go to Layer > Simplify Layer and you should now be able to edit the image

ERROR:EDK:4182, ERROR:EDK:4075 & 4073 Miscellaneous Errors that occur when adding cores

So I ran into some interesting errors when adding simple cores to my design. On ISE13.2 working with the ML510 I encountered these errors when adding one simple core. 

At first I started out with a set of errors that looked like this:

 ----------------------------------------
ERROR:EDK:4182 - PORT:PLB_masterID - VEC evaluation of (C_SPLB_MID_WIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\data_checker_v1_00_a\data\data_checker_v2_1_0.mpd line 51

ERROR:EDK:4182 - PORT:PLB_BE - VEC evaluation of ((C_SPLB_DWIDTH/8)-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\data_checker_v1_00_a\data\data_checker_v2_1_0.mpd line 55

ERROR:EDK:4182 - PORT:PLB_wrDBus - VEC evaluation of (C_SPLB_DWIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\data_checker_v1_00_a\data\data_checker_v2_1_0.mpd line 60

ERROR:EDK:4182 - PORT:Sl_rdDBus - VEC evaluation of (C_SPLB_DWIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\data_checker_v1_00_a\data\data_checker_v2_1_0.mpd line 76

ERROR:EDK:4182 - PORT:PLB_masterID - VEC evaluation of (C_SPLB_MID_WIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\rx_serdes_v1_00_a\data\rx_serdes_v2_1_0.mpd line 57

ERROR:EDK:4182 - PORT:PLB_BE - VEC evaluation of ((C_SPLB_DWIDTH/8)-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\rx_serdes_v1_00_a\data\rx_serdes_v2_1_0.mpd line 61

ERROR:EDK:4182 - PORT:PLB_wrDBus - VEC evaluation of (C_SPLB_DWIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\rx_serdes_v1_00_a\data\rx_serdes_v2_1_0.mpd line 66

ERROR:EDK:4182 - PORT:Sl_rdDBus - VEC evaluation of (C_SPLB_DWIDTH-1) failed - C:\Users\user1\Documents\Projects4\v2\pcores\rx_serdes_v1_00_a\data\rx_serdes_v2_1_0.mpd line 82
  ----------------------------------------

 To get around this, most of the time you see a VEC evaluation failed, you can just hardcode the values in the .mpd file to what they should be. When you do this you clear these but you get another set of errors as depicted below.

 ----------------------------------------
ERROR:EDK:4075 - INSTANCE: DDR2_SDRAM_DIMM1, PORT: SPLB0_Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v6_04_a\data\mpmc_v2_1_0.mpd line 1013
ERROR:EDK:4075 - INSTANCE: PCI32_BRIDGE, PORT: Sl_RdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pci_v1_04_a\data\plbv46_pci_v2_1_0.mpd line 191
ERROR:EDK:4075 - INSTANCE: SysACE_CompactFlash, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\data\xps_sysace_v2_1_0.mpd line 121
ERROR:EDK:4075 - INSTANCE: mdm_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 159
ERROR:EDK:4075 - INSTANCE: xps_intc_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_01_a\data\xps_intc_v2_1_0.mpd line 130
ERROR:EDK:4075 - INSTANCE: blink_test_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Users\user1\Documents\Projects4\v2\pcores\blink_test_v1_00_a\data\blink_test_v2_1_0.mpd line 72

ERROR:EDK:4075 - INSTANCE: data_gen_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Users\user1\Documents\Projects4\v2\pcores\data_gen_v1_00_a\data\data_gen_v2_1_0.mpd line 75

ERROR:EDK:4075 - INSTANCE: tx_serdes_0, PORT: Sl_rdDBus, CONNECTOR: mb_plb_Sl_rdDBus - calculated index is out of signal VEC range of [0:1087] - C:\Users\user1\Documents\Projects4\v2\pcores\tx_serdes_v1_00_a\data\tx_serdes_v2_1_0.mpd line 79

ERROR:EDK:4073 - INSTANCE: mb_plb, PORT: PLB_BE, CONNECTOR: mb_plb_PLB_BE - 16 bit-width connector assigned to 8 bit-width port - C:\Users\user1\Documents\Projects4\v2\_xps_tempmhsfilename.mhs line 112

ERROR:EDK:4073 - INSTANCE: mb_plb, PORT: PLB_masterID, CONNECTOR: mb_plb_PLB_masterID - 3 bit-width connector assigned to 2 bit-width port - C:\Users\user1\Documents\Projects4\v2\_xps_tempmhsfilename.mhs line 112

ERROR:EDK:4073 - INSTANCE: mb_plb, PORT: PLB_wrDBus, CONNECTOR: mb_plb_PLB_wrDBus - 128 bit-width connector assigned to 64 bit-width port - C:\Users\user1\Documents\Projects4\v2\_xps_tempmhsfilename.mhs line 112
----------------------------------------

These errors are fairly bizarre since I didn't really touch anything. To fix the errors, simply ignore the beginning ones about VEC signal out of range, and jump straight to the last ones at the end about the PORTS. The trick is to manually change the the widths in the .mpd to the values the errors are requesting.

Reconfiguring Zynq Processing System Settings and Clocks

I thought I would post this because someone was asking me about the Zynq FCLKs today. To determine the max frequency of the Zynq clocks you can access the "Clock Wizard" in XPS. You can customize and configure much of the pre-defined cores that are automatically added to most Zynq projects from the "Zynq" tab:

To check out the clock settings, click the box that says "Clock Generation" this core specifically configures the PS to PL available clocks.
Once you click this the "Clock Wizard" will appear. You can now see what the frequencies of the different clocks are.