If you are designing a core that goes inside the design you can safely ignore this error.
What it means is the number of pins at the top level is more than the total available pins of the design, that's why it happens during the implement design phase.
Map fails because the selected FPGA doesn't have enogh resources (I/O pins).
See this Thread:
http://www.edaboard.com/thread205544.html
No comments:
Post a Comment