Export Bistream Setting Greyed out when Implementation is open

So 14.7 does this annoying thing where you cannot export the bitstream unless the implementation is open, it gets even worse where sometimes you can have the option still greyed out even if the implementation is open, when this happens the tools didn't make the run you wanted the active run so you need to change it to be able to export

Error: EDK:3759 AddressGen MHS

ERROR:EDK:3759 - AddresGen MHS Error Address Generator can not generate address map for your design. Please check if there is address conflict, clear the conflict and re-generate the address map.Please consult the online help for how to let Address Generator to overwrite the address. If Address Generator still can not generate the address map, please provide the address map manually.
axi_plbv46_bridge_1 has been deleted from the project


So the setup here is I was try to add one normal core that just connects to an axi, and then another core that connects to a plb that also connects to an axi, so axi-to-plb bridge

ISE 14.7

Here are the steps to make it work:

1. Add just the core that only connects the that axi first and then click the address gen button
2. For the Axi-to-plb bridge core, first add the core, set the address
3. Then add the bridge, the bridge MUST be connected to the same interconnect as any other bridges of the same type

Yea this one is frustrating. 

Xilinx SDK Running .elf on the DDR

So I was having problems with this earlier.

The program I was running was too big to fit in the BRAM:

ERROR:EDK:3165 - elfcheck failed!
The following sections did not fit into Processor BRAM memory:
 Section .data (0x420109C0 - 0x42012587)
 Section .rodata (0x4200FF10 - 0x420109BB)
 Section .dtors (0x4200FF08 - 0x4200FF0F)
 Section .ctors (0x4200FF00 - 0x4200FF07)
 Section .fini (0x4200FEE0 - 0x4200FEFF)
 Section .init (0x4200FEA4 - 0x4200FEDF)
 Section .text (0x42000000 - 0x4200FEA3)

Try using the linker script generation tools to generate an ELF that maps
correctly to your hardware design.

 So That is kind of annoying, you now have two options, either 1) make the bram bigger or 2) run it in the DDR

I found the following posts, all kind of describing what was needed to run it in the DDR.

1. Link1
2. Link2
3. Link3

Here is what worked for me:

1. Make sure to generate a new linker with everything in the DDR
2. Program the system.bit and system.bmm with the "Program FPGA" button, make sure that for the "software configuration" that "bootloop" is selected
3. Open the XMD with Xilinx Tools >  XMD Console 
4. when it opens you should have seen a programming FPGA status line: "Fpga Programming Progress....10......etc
5. Type in the following commands

For the Power PC

connect ppc hw  
cd "c:\Location_to_your_software_debug_folder"
dow "your_elf_file" 
con

remember that if the processor is acting weird you can always do a
connect ppc hw; stop; rst -processor

then continue on from dow

Xilinx running someone else's SDK Project

Recently, I had a problem with someone giving me an SDK project.

Here are some useful steps to getting their crap to work

1. Make sure you have your license server on or the bsp will not build
2. If the bsp does not build create a new "Hello World" project and BSP
3. Go to Xilinx Tools > "Repositories" and add in their custom MyProcessorIPLib to nab their drivers
4. Right click on the BSP and "Board Support Package Settings" Make sure the Correct "Supported Libraries" are checked off 
5. Click on the "Drivers" tab and make sure all the correct drivers are loaded instead of the generic 
6. Copy over their source files 
7. Rebuild the project

printf & xil_printf statements break when printing values

I was doing some dev work on the ML507 and I kept running into this problem where the printf statements would not print variables using stuff like %08x and %d etc...

Turns out I needed to change the size of the stack and heap to 0x2000 from 0x400.

more of this error detailed here: Link!