Error: [Common 17-36] Cannot write file [project_constraints.ucf]

http://forums.xilinx.com/t5/Hierarchical-Design/PlanAhead-cannot-write-to-ucf-during-runs/td-p/271092


I ran into this when I was copying over projects and just modifying the constraints. The solution is to: A workaround for this specific issue is to uncheck "Read- only" for the UCF file that resides in the folder <project_name>.runs/impl_1/.constrs

>> 11/25 Update

Okay this also sometimes happens to me even when the Read-Only IS unchecked, when that happens, I saw one poster that deleted the folder for the run (impl_1 typically) I just made a new run and it will go.

UART not responding on working SDK project and Bitstream

When you need UARTs to connect to peripheral devices as well as UARTs to the terminal, you can run into many confusing situations. In my case I was getting no UART output. One of the things that worked for me was modifying the bsp settings

See the steps below:

Program FPGA Failed: DONE bit didn't go high after programming FPGA

So I ran into this problem for the first time today:

The issue ended up being that while debugging I had to relaunch the SDK and it auto defaulted to the wrong bitfile, so the entire time I was attempting to program the wrong bitstream.

This can also happen if you were previously automatically booting from Linux like with a NAND or something, just program again 

Failed to launch program edif2ngd

[NgdBuild 527] Failed to launch program edif2ngd: The pipe has been ended.

[NgdBuild 28] edif2ngd did not successfully complete.  Please check preceding errors for root cause.

 

This error sucked. Turns out you just need to re-launch the implementation run again. Didn't do anything special.